A microelectronic device may include electrical interconnections for transferring electrical signals. These interconnections are typically formed by patterning conductive layers, and these interconnections may influence the operating speed of the microelectronic device. Multi-layered interconnection technologies have thus been developed to reduce the length of interconnections to thereby improve operating speeds of microelectronic devices. The multi-layered interconnection technologies can also reduce the size of a microelectronic device thus facilitating higher levels of device integration.
In particular, multi-layered interconnections can be provided by forming an interlayer insulating layer between upper and lower interconnections. The interlayer insulating layer is preferably planarized at a low temperature so that the characteristics of electronic devices such as transistors are not significantly changed. The interlayer insulating layer is also preferably formed of a material having a relatively low dielectric constant to reduce parasitic capacitances between adjacent interconnections.
Spin-on-glass layers have been used to provide interlayer insulating layers which can be planarized at relatively low temperatures and provide relatively low dielectric constants. A spin-on-glass interlayer insulating layer can be formed by coating a liquid spin-on-glass based material on the microelectronic device including the lower interconnection and hardening a spin-on-glass layer by baking it at a predetermined temperature. Contact holes can be formed in the interlayer insulating layer exposing portions of the lower interconnections. The upper interconnections can be formed on the interlayer insulating layer with contact to the lower interconnections provided through the contact holes.
A spin-on-glass layer, however, may exhibit a relatively strong hygroscopicity. In other words, a spin-on-glass layer may absorb moisture. If moisture is absorbed into the spin-on-glass layer, a wet-etch rate of the spin-on-glass layer may increase, and the dielectric constant may also increase. Accordingly, a wet-etch used to remove a natural oxide on portions of the lower interconnection exposed by the contact holes may have an increased etch rate due to the absorption of moisture. Accordingly, the spin-on-glass interlayer insulating layer may be undesirably etched when removing the natural oxide from the lower interconnection so that the size of the contact hole is undesirably increased. In addition, parasitic capacitances between adjacent interconnections may increase if moisture is absorbed by the spin-on-glass interlayer insulating layer. An operating speed of the microelectronic device may thus decrease due to the increased parasitic capacitances.
A quantity of moisture absorbed by a spin-on-glass interlayer insulating layer can be reduced by thermally treating the spin-on-glass layer at a temperature greater than 800.degree. C. A thermal treatment at a temperature greater than 800.degree. C., however, may change the characteristics of transistors formed under the spin-on-glass layer. In particular, this thermal treatment may reduce channel lengths as a result of re-diffusion of dopants in the source/drain and channel regions thus altering the dopant concentrations of the transistor channel regions. Accordingly, there continues to exist a need in the art for improved interlayer insulating layers and methods for forming microelectronic devices.